1. Field Of The Invention
This invention relates to the field of semiconductor device fabrication and more specifically to a process designed to etch contact openings or vias in an insulative layer.
2. Prior Art
In the manufacture of semiconductor devices, there is a need to make electrical contact to certain regions of the device. For example, in a wide variety of devices such as MOS transistors, EPROMS, capacitors, etc., electrical contact must be made to various regions including diffusion regions in the semiconductor substrate such as source or drain diffusions, and polysilicon gates. In addition, it is usually necessary to make electrical contact to other structures of the device as well, for example, to the first metalization. Normally, the regions which must be contacted are completely covered with a dielectric layer during fabrication which is deposited to provide electrical isolation. Electrical contact is made to the above described regions by first forming an opening in the dielectric over the contact region or metal layer and next filling the opening with a conductive material. The openings can be filled in the same step in which interconnects are formed, for example, by depositing a blanket layer of aluminum, forming a masking layer to cover the openings, as well as the regions which will become interconnects, and then etching the exposed aluminum. The above described processing fills the opening with aluminum and forms interconnects which are necessary for functioning of the device. Alternatively, the opening can be filled in a separate process followed by aluminium deposition, masking, and etch to form interconnects which contact the fill material.
Generally, when etching an opening in a dielectric layer overlying a contact region such as a source, drain, or gate, the process is referred to as the "contact etch", and the openings thus formed are called contact openings. When etching an opening in a dielectric layer overlying, for example, a metal layer to be contacted, the process is referred to as the "via etch", and the openings thus formed are called vias.
Various types of insulative layers are formed at several different process steps during fabrication. Thermal oxide of approximately 5000-6000 .ANG. is grown as field isolation relatively early in the processing. Later, a gate oxide is formed. Then, through a sequence of steps, the gate is formed and diffusion regions are defined within the substrate. Next, a borophosphosilicate glass (BPSG) inter-level dielectric layer is deposited on the substrate. It is through this BPSG layer which the contact openings must be made. It addition to the BPSG layer, there may be other oxide layers overlying the contact regions. For example, the source and drain may still be covered with the gate oxide, a pad oxide layer, or a sacrificial oxide layer. In CMOS devices, there may be a low temperature oxide (LTO) between the contact regions and the BPSG layer to prevent counter-doping. If any of these other oxides are present, they are etched in the same step as the BPSG layer. Generally, these layers are much thinner than the BPSG layer. In the present discussion, it will be assumed that the BPSG layer is deposited directly on the contact region. However, the presence of these additional layers will not affect the practice of the present invention as described herein.
In order to form the contact openings, a masking material such as photoresist is formed over the entire BPSG layer. The resist is patterned by well known methods to expose openings in the BPSG layer over the contact regions. Additionally, the BPSG layer is exposed in other regions, such as in the scribe lines between die and, for example, portions of the mask alignment mark region to allow for alignment with subsequent layers. Next, the dielectric layer is etched in the exposed regions to form the contact openings.
In the prior art, various dry etching processes are used to etch the oxide. Although oxide can be wet etched in a solution containing hydrofluoric acid (HF), dry processes are preferred since they are non-intrusive (since the wafers do not need to be submerged in an acid solution) and do not have the undercutting problems associated with wet etches. Nearly all modern processes use dry etches or wet/dry etches to etch oxide layers. The dry processes are carried out by plasma etching or reactive ion etching (RIE). Typical gasses used in dry processes include oxygen and various halocarbons, particularly chloro and/or fluoro carbons such as CHF.sub.3 (Freon 23), C.sub.3 F.sub.8, C.sub.2 F.sub.6, and CF.sub.4. Other halogenated compounds such as NF.sub.3, SF.sub.6, SiF.sub.4, and SiF.sub.2 may also be used. In addition, other gasses such as A.sub.r, He, N.sub.2, H.sub.2, Cl.sub.2 and F.sub.2 are often added to the gas flow. The particular gas mixture used will depend on, for example, the characteristics of the oxide being etched, the stage of processing, the etch tool being used, the desired etch characteristics such as etch rate, wall slope, anisotropy, etc.
One problem with the above-mentioned dry etching processes for etching oxides is the occurrence of the "micro masking" effect. This effect occurs most commonly when etching a BPSG layer in a dry process, and occurs mostly in large open sites on the wafer. Generally, very little micro masking occurs in the contact openings. Although the exact cause of the phenomena is not known, is believed that during the plasma etch some cross-linking occurs to form a polymer on the surface of the BPSG layer which is resistant to the etch. FIG. 1 shows an example of the result of a prior art dry etching process. FIG. 1 shows the top view of a portion of a semiconductor substrate after BPSG deposition, masking, and etch. In the contact regions where the contact openings will be formed (not shown in FIG. 1), the BPSG is deposited directly on top of the contact regions, for example, directly on top of a source region. In the region shown in FIG. 1, the BPSG film is deposited on top of a thermal oxide. The inner region 10 was left unmasked in order to etch all BPSG from region 10 as well as some of the underlying thermal oxide. The outer region 11 is unetched BPSG which was masked by photoresist during the etching process. As can be seen, within inner region 10 there are a plurality of micro masking defects 15. Each micro masking defect 15 has a diameter of approximately 0.5 microns and a height of approximately 0.2-0.3.mu.. However, the size and the shape of the micro masking defects 15 can vary.
Surrounding the micro masking defects 15 is a clear surface 16 of underlying oxide which has been completely cleared of the BPSG layer during the etch. Usually, the inner region 10 of an open site such as that shown in FIG. 1 would be used to measure the total oxide thickness removed, in order to determine etch rates and to ensure adequate overetch. Region 10 is used since the contact openings themselves are too small in diameter to permit measurement of remaining oxide in those regions. Also, since the BPSG is on top of a relatively thick thermal oxide in the open regions shown in FIG. 1, overetch can be determined. That is, by measuring the remaining oxide in region 10, the amount of thermal oxide removed after the BPSG layer has been removed can be determined, giving an indication of the extent of overetch of the BPSG layer.
The micro masking problem illustrated in FIG. 1 causes several problems. The presence of a large number of micro masking defects 15 causes light to be reflected randomly or scattered from the surface. Because of this scattering, film thickness of the remaining oxide in region 10 cannot be determined accurately. This is due to the fact that analytical instruments for measuring film thickness shine an optical beam through the film and measure the intensity of the reflected beam to determine film thickness. Since the remaining film thickness in these areas cannot be measured, on-line determination of the amount of oxide removed, and the etch rate cannot be made. The lack of on-line measurement is a serious detriment as process control is much more difficult without the availability of on-line data with which to control the process. Finally, the micro masking defects 15 make surface features harder to see through a microscope such as an alignment microscope. Thus, alignment of subsequent layers is more difficult due to the presence of the micro masking defects 15.
What is needed is a process to etch a BPSG layer from contact openings which does not create micro masking defects in large open areas so that film thickness can be measured reliably, etch parameters can be measured on-line, and alignment to subsequent layers is not impeded.